Flip-chip bonding is one method currently used in the semiconductor industry to physically and electrically connect a semiconductor die to the next level of interconnection wiring. Solder bumps are deposited on the bonding pads of a semiconductor die, and these solder bumps are then soldered to traces on the next level interconnect to link the die's internal functional portions to the next level interconnect. Typically, solder bumping and wafer probe test is done at the wafer level before the die are sent to assembly and test.
There is a strong effort in the semiconductor industry for providing known good die (KGD) for flip-chip applications. This means that the semiconductor dice must be tested in order to verify functionality and then burned-in, usually by probing at an elevated temperature and with electrical bias to identify acceptable product. However, the presence of the solder bumps on the semiconductor wafer presents difficulties at both test and burning. Since the solder bumps are composed of lead and tin, they are fairly ductile and thus tend to deform during probing. This problem is exacerbated when the probing is done at elevated temperatures, because the solder bumps become even softer at the higher temperatures and deform more easily. A wafer reflow step can be performed after probing in an effort to regain the round bump shape, but if the deformation is extensive, the additional reflow step cannot cure this defect. In addition, the reflow step is a cost adder. Another problem with the present method of probing bumped semiconductor wafers is that bump height variations across the wafer can cause some false readings of failures so that good die may erroneously be discarded due to false test results. Furthermore, lead oxide (Pb.sub.x O.sub.y) from the solder bumps tends to stick to the probe tips thus requiring cleaning of the probe tips to eliminate the risk of contamination.
Thus a need exists for a method to easily test flip-chip semiconductor dice prior to assembly for KGD applications.